FPGA Design Verification Engineer

Responsibilities and Duties:

As a key member of our FPGA team, you will play an important role in verifying the design and implementation of the industry's leading network monitoring devices.

• Responsible for hands-on verification of FPGA designs using state of the art verification methodologies such as UVM.

• Architect and develop testbench components in SystemVerilog UVM environment.

• Write constrained random tests and execute test plans for design under test.

• Debug failures and root cause issues.

• Perform coverage analysis and drive to coverage closure.

• Integrate verification into continuous integration flow and into CI tools like TeamCity.

• Work closely with the Software and QA teams to plan and prioritize tasks.

• Mentor junior engineers and interns.

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Qualifications and Skills:

• Bachelor's degree in EE/CS/CE or equivalent, with 7+ years of relevant experience, or Master’s degree in EE/CS/CE or equivalent, with 5+ years of relevant experience

• UVM and SystemVerilog expertise.

• Networking and packet processing experience preferred.

• Strong debugging, troubleshooting and analytical skills.

• Strong communication skills and collaborative attitude.

• Self-starter, and motivated to champion continuous improvement and positive team culture.

• Python experience is desirable.

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